This invention relates in general to digital counters and more specifically to an efficient functional test scheme incorporated into a programmable duration binary counter.
Digital counters are used in a variety of applications ranging from data communication to digital processing systems. Basically, a digital counter receives at its input an enable signal. Each time this signal is received along with a clock signal, the counter increments or decrements its output by one. As a result, such counting devices can have a plurality of values, depending upon the number of bits that the counter is capable of storing.
It is often necessary to test counters for proper operation. Counters and other components are generally tested before shipment to a customer, but also can be tested by the customer upon delivery of the electronic equipment. Testing of counting devices is especially important to insure proper carry operation during incrementing. That is, when a binary 1 is added to a binary 1 already stored in a given bit location, the next significant bit must be incremented as a result of the carry thereto. Also, it is important to determine whether every bit of a counter can toggle properly. If a bit is stuck at zero, for example, then obviously operation of the entire counter is suspect.
In a number of applications, such as when the clock signal has a high frequency, the counter's ability to increment at high speeds becomes very important. Therefore, in addition to testing the counting functionality of the counter, it is also important to test the counter to insure that the counter is capable of operating properly at its maximum specified operating frequency.
Lastly, many of today's counters are able to be loaded with a predetermined value before commencement of the counting operation. In such counters, it is important to also test the loading functionality of the counter to ensure that each bit of the counter may be loaded with either a 1 or a zero.
Traditionally, every value of which a counter is capable of storing is tested individually and sequentially. This has been a time consuming process. For example, if a counter has 16 bits, the testing operation must be performed for each of the 2.sup.16 combinations to ensure that all values have been properly tested and that all bits have been evaluated for toggling as a consequence of the natural carry process. In addition, where the counter to be tested is loadable, each bit within the counter must be tested to ensure that it is capable of loading both a 1 and a zero. For a 16-bit counter, this testing of the loading functionality would typically require an additional 2.sup.16 +2 clock cycles in the case where the values loaded into the counter can only be verified by having the counter count down/up until the counter is empty/full.
It should be appreciated that often many relatively large counters are present in an integrated circuit chip and that a great number of integrated circuit chips are used in larger systems. Thus, the amount of time spent testing systems is directly dependent on, inter alia, the time it takes to test a counter thoroughly. Similarly, during the counter manufacturing process, it is common to test a significant number or all of the manufactured counters in order to ensure that each counter is working properly before shipping.
One objective of the present invention, therefore, is to provide a testing process for a counter that works efficiently-and quickly. Another objective is to provide a testing system for a counter that requires a minimum of additional logic circuitry. Yet another objective is to provide a counter tester that would operate in less time than conventional testers which require sequential accessing of every value in the counter. A final objective of the present invention is to provide a system that requires minimal programming of test bits to test the counter completely.